They are complementary. Each new instruction set extension add new instructions and eventually a new programming model (new registers for example). None are deprecated, deprecating instructions is almost impossible to do for compatibility reasons. However some optional extensions may be absent or removed from newer models (like the FMA4 of AMD) if not very wide … Read more
A gate (call, interrupt, task or trap) is used to transfer control of execution across segments. Privilege level checking is done differently depending on the type of destination and instruction used. A call gate uses the CALL and JMP instructions. Call gates transfer control from lower privilege code to higher privilege code. The gate DPL … Read more
x86 is a CISC architecture. The number of instructions is a big factor as all cisc architectures with all more instructions. Furthermore as instructions are complex in cisc they can take >1 cycle to complete, where as in RISC they should be single cycle. The main differences are found here: +——————————+——————————+ | CISC | RISC … Read more
Largely, for the same reason you start at the least significant digit (the right end) when you add—because carries propagate toward the more significant digits. Putting the least significant byte first allows the processor to get started on the add after having read only the first byte of an offset. After you’ve done enough assembly … Read more
C has div and ldiv. Whether these generate separate instructions for the quotient and remainder will depend on your particular standard library implementation and compiler and optimization settings. Starting with C99, you also have lldiv for larger numbers.
Hans and DarkDust answer covered i386/i686 and amd64/x86_64, so there’s no sense in revisiting them. This answer will focus on X32, and provide some info learned after a X32 port. x32 is an ABI for amd64/x86_64 CPUs using 32-bit integers, longs and pointers. The idea is to combine the smaller memory and cache footprint from … Read more
Here is an article over at software.intel.com on that sheds little light on user level locks: User level locks involve utilizing the atomic instructions of processor to atomically update a memory space. The atomic instructions involve utilizing a lock prefix on the instruction and having the destination operand assigned to a memory address. The following … Read more
This is what you are looking for: Assemblers And Loaders – By David Salomon. Published February, 1993 – Freely available (download here) Of course, you are going to need the following: Intel® 64 and IA-32 Architectures Software Developer’s Manuals AMD-64 Architecture Programmers manual Linkers and Loaders by John R. Levine (freely available) ELF File Format … Read more
TL:DR: int 0x80 works when used correctly, as long as any pointers fit in 32 bits (stack pointers don’t fit). But beware that strace decodes it wrong unless you have a very recent strace + kernel. int 0x80 zeros r8-r11 for reasons, and preserves everything else. Use it exactly like you would in 32-bit code, … Read more
When people refer to 32-bit and 64-bit assembly, they’re talking about which instruction set you’ll use – they’re also sometimes called Ia32 and x64 in the Intel case, which I presume you’re asking about. There is a lot more going on in the 64-bit case, so starting with 32-bit is probably good; you just need … Read more